/*
 * Copyright (c) 2012, Freescale Semiconductor, Inc.
 * All rights reserved.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

// File: spdif_iomux_config.c

/* ------------------------------------------------------------------------------
 * <auto-generated>
 *     This code was generated by a tool.
 *     Runtime Version:3.4.0.0
 *
 *     Changes to this file may cause incorrect behavior and will be lost if
 *     the code is regenerated.
 * </auto-generated>
 * ------------------------------------------------------------------------------
*/

#include "iomux_config.h"
#include "registers/regsiomuxc.h"

// Function to configure IOMUXC for spdif module.
void spdif_iomux_config(void)
{
    // Config spdif.SPDIF_EXT_CLK to pad RGMII_TXC(D21)
    // HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_WR(0x00000002);
    // HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_WR(0x00003000);
    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(0x00080000);
    // HW_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_WR(0x00000000);
    // Mux Register:
    // IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC(0x020E0058)
    //   SION [4] - Software Input On Field Reset: DISABLED
    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
    //     ENABLED (1) - Force input path of pad.
    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
    //                    Select iomux modes to be used for pad.
    //     ALT0 (0) - Select instance: usb signal: USB_H2_DATA
    //     ALT1 (1) - Select instance: enet signal: RGMII_TXC
    //     ALT2 (2) - Select instance: spdif signal: SPDIF_EXT_CLK
    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO19
    //     ALT7 (7) - Select instance: xtalosc signal: XTALOSC_REF_CLK_24M
    HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_WR(
            BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_SION_V(DISABLED) | 
            BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_MUX_MODE_V(ALT2));
    // Pad Control Register:
    // IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC(0x020E036C)
    //   DDR_SEL_RGMII [19:18] - DDR Select Field Reset: RESERVED0
    //                           NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register.
    //                           Note: The value of this field does not reflect the vaule of the
    //                           IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register.
    //     RESERVED0 (0) - Reserved
    //     RESERVED1 (1) - Reserved
    //     1P2V_IO (2) - 1.2V I/O interfaces including USB HSIC and MIPI_HSI. Provides calibrated drive strengths for signals ranging from 1.0V up to 1.3V.
    //     1P5V_IO (3) - 1.5V I/O interfaces including ENET. Provides calibrated drive strengths for signals ranging from 1.3V to 2.5V.
    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
    //     DISABLED (0) - CMOS input
    //     ENABLED (1) - Schmitt trigger input
    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
    //     100K_OHM_PD (0) - 100K Ohm Pull Down
    //     47K_OHM_PU (1) - 47K Ohm Pull Up
    //     100K_OHM_PU (2) - 100K Ohm Pull Up
    //     22K_OHM_PU (3) - 22K Ohm Pull Up
    //   PUE [13] - Pull / Keep Select Field Reset: PULL
    //     KEEP (0) - Keeper Enabled
    //     PULL (1) - Pull Enabled
    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
    //     DISABLED (0) - Pull/Keeper Disabled
    //     ENABLED (1) - Pull/Keeper Enabled
    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
    //                NOTE: Read Only Field
    //                The value of this field is fixed and cannot be changed.
    //     DISABLED (0) - Disabled
    //     120_OHM (1) - 120 Ohm ODT
    //     60_OHM (2) - 60 Ohm ODT
    //     40_OHM (3) - 40 Ohm ODT
    //     30_OHM (4) - 30 Ohm ODT
    //     RESERVED0 (5) - Reserved
    //     20_OHM (6) - 20 Ohm ODT
    //     RESERVED1 (7) - Reserved
    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
    //     HIZ (0) - HI-Z
    //     240_OHM (1) - 240 Ohm
    //     120_OHM (2) - 120 Ohm
    //     80_OHM (3) - 80 Ohm
    //     60_OHM (4) - 60 Ohm
    //     48_OHM (5) - 48 Ohm
    //     40_OHM (6) - 40 Ohm
    //     34_OHM (7) - 34 Ohm
    HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_WR(
            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_HYS_V(DISABLED) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUS_V(100K_OHM_PD) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUE_V(PULL) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PKE_V(ENABLED) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DSE_V(HIZ));
    // Pad Group Control Register:
    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII(0x020E0790)
    //   DDR_SEL_RGMII [19:18] - DDR Select Field Reset: 1P2V_IO
    //     RESERVED0 (0) - Reserved
    //     RESERVED1 (1) - Reserved
    //     1P2V_IO (2) - 1.2V I/O interfaces including USB HSIC and MIPI_HSI. Provides calibrated drive strengths for signals ranging from 1.0V up to 1.3V.
    //     1P5V_IO (3) - 1.5V I/O interfaces including ENET. Provides calibrated drive strengths for signals ranging from 1.3V to 2.5V.
    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(
            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII_V(1P2V_IO));
    // Pad RGMII_TXC is involved in Daisy Chain.
    // Input Select Register:
    // IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT(0x020E0918)
    //   DAISY [0] - MUX Mode Select Field Reset: RGMII_TXC_ALT2
    //               Selecting Pads Involved in Daisy Chain.
    //     RGMII_TXC_ALT2 (0) - Select signal spdif SPDIF_EXT_CLK as input from pad RGMII_TXC(ALT2).
    //     ENET_CRS_DV_ALT3 (1) - Select signal spdif SPDIF_EXT_CLK as input from pad ENET_CRS_DV(ALT3).
    HW_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_WR(
            BF_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_DAISY_V(RGMII_TXC_ALT2));

    // Config spdif.SPDIF_IN to pad KEY_COL3(U5)
    // HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_WR(0x00000006);
    // HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_WR(0x00003000);
    // HW_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_WR(0x00000002);
    // Mux Register:
    // IOMUXC_SW_MUX_CTL_PAD_KEY_COL3(0x020E0210)
    //   SION [4] - Software Input On Field Reset: DISABLED
    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
    //     ENABLED (1) - Force input path of pad.
    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
    //                    Select iomux modes to be used for pad.
    //     ALT0 (0) - Select instance: ecspi1 signal: ECSPI1_SS3
    //     ALT1 (1) - Select instance: enet signal: ENET_CRS
    //     ALT2 (2) - Select instance: hdmi signal: HDMI_TX_DDC_SCL
    //     ALT3 (3) - Select instance: kpp signal: KEY_COL3
    //     ALT4 (4) - Select instance: i2c2 signal: I2C2_SCL
    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO12
    //     ALT6 (6) - Select instance: spdif signal: SPDIF_IN
    HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_WR(
            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION_V(DISABLED) | 
            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE_V(ALT6));
    // Pad Control Register:
    // IOMUXC_SW_PAD_CTL_PAD_KEY_COL3(0x020E05E0)
    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
    //     DISABLED (0) - CMOS input
    //     ENABLED (1) - Schmitt trigger input
    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
    //     100K_OHM_PD (0) - 100K Ohm Pull Down
    //     47K_OHM_PU (1) - 47K Ohm Pull Up
    //     100K_OHM_PU (2) - 100K Ohm Pull Up
    //     22K_OHM_PU (3) - 22K Ohm Pull Up
    //   PUE [13] - Pull / Keep Select Field Reset: PULL
    //     KEEP (0) - Keeper Enabled
    //     PULL (1) - Pull Enabled
    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
    //     DISABLED (0) - Pull/Keeper Disabled
    //     ENABLED (1) - Pull/Keeper Enabled
    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
    //              Enables open drain of the pin.
    //     DISABLED (0) - Output is CMOS.
    //     ENABLED (1) - Output is Open Drain.
    //   SPEED [7:6] - Speed Field Reset: 100MHZ
    //     TBD (0) - TBD
    //     50MHZ (1) - Low (50 MHz)
    //     100MHZ (2) - Medium (100 MHz)
    //     200MHZ (3) - Maximum (200 MHz)
    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
    //     HIZ (0) - HI-Z
    //     240_OHM (1) - 240 Ohm
    //     120_OHM (2) - 120 Ohm
    //     80_OHM (3) - 80 Ohm
    //     60_OHM (4) - 60 Ohm
    //     48_OHM (5) - 48 Ohm
    //     40_OHM (6) - 40 Ohm
    //     34_OHM (7) - 34 Ohm
    //   SRE [0] - Slew Rate Field Reset: SLOW
    //             Slew rate control.
    //     SLOW (0) - Slow Slew Rate
    //     FAST (1) - Fast Slew Rate
    HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_WR(
            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS_V(DISABLED) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS_V(100K_OHM_PD) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE_V(PULL) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE_V(ENABLED) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE_V(DISABLED) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED_V(TBD) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE_V(HIZ) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE_V(SLOW));
    // Pad KEY_COL3 is involved in Daisy Chain.
    // Input Select Register:
    // IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT(0x020E0914)
    //   DAISY [1:0] - MUX Mode Select Field Reset: EIM_DATA21_ALT7
    //                 Selecting Pads Involved in Daisy Chain.
    //     EIM_DATA21_ALT7 (0) - Select signal spdif SPDIF_IN as input from pad EIM_DATA21(ALT7).
    //     ENET_RX_ER_ALT3 (1) - Select signal spdif SPDIF_IN as input from pad ENET_RX_ER(ALT3).
    //     KEY_COL3_ALT6 (2) - Select signal spdif SPDIF_IN as input from pad KEY_COL3(ALT6).
    //     GPIO16_ALT4 (3) - Select signal spdif SPDIF_IN as input from pad GPIO16(ALT4).
    HW_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_WR(
            BF_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY_V(KEY_COL3_ALT6));

    // Config spdif.SPDIF_LOCK to pad ENET_MDIO(V23)
    // HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_WR(0x00000006);
    // HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_WR(0x000000B1);
    // Mux Register:
    // IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO(0x020E01D0)
    //   SION [4] - Software Input On Field Reset: DISABLED
    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
    //     ENABLED (1) - Force input path of pad.
    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
    //                    Select iomux modes to be used for pad.
    //     ALT1 (1) - Select instance: enet signal: ENET_MDIO
    //     ALT2 (2) - Select instance: esai signal: ESAI_RX_CLK
    //     ALT4 (4) - Select instance: enet signal: ENET_1588_EVENT1_OUT
    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO22
    //     ALT6 (6) - Select instance: spdif signal: SPDIF_LOCK
    HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_WR(
            BF_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_SION_V(DISABLED) | 
            BF_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_MUX_MODE_V(ALT6));
    // Pad Control Register:
    // IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO(0x020E04E4)
    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
    //     DISABLED (0) - CMOS input
    //     ENABLED (1) - Schmitt trigger input
    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
    //     100K_OHM_PD (0) - 100K Ohm Pull Down
    //     47K_OHM_PU (1) - 47K Ohm Pull Up
    //     100K_OHM_PU (2) - 100K Ohm Pull Up
    //     22K_OHM_PU (3) - 22K Ohm Pull Up
    //   PUE [13] - Pull / Keep Select Field Reset: PULL
    //     KEEP (0) - Keeper Enabled
    //     PULL (1) - Pull Enabled
    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
    //     DISABLED (0) - Pull/Keeper Disabled
    //     ENABLED (1) - Pull/Keeper Enabled
    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
    //              Enables open drain of the pin.
    //     DISABLED (0) - Output is CMOS.
    //     ENABLED (1) - Output is Open Drain.
    //   SPEED [7:6] - Speed Field Reset: 100MHZ
    //     TBD (0) - TBD
    //     50MHZ (1) - Low (50 MHz)
    //     100MHZ (2) - Medium (100 MHz)
    //     200MHZ (3) - Maximum (200 MHz)
    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
    //     HIZ (0) - HI-Z
    //     240_OHM (1) - 240 Ohm
    //     120_OHM (2) - 120 Ohm
    //     80_OHM (3) - 80 Ohm
    //     60_OHM (4) - 60 Ohm
    //     48_OHM (5) - 48 Ohm
    //     40_OHM (6) - 40 Ohm
    //     34_OHM (7) - 34 Ohm
    //   SRE [0] - Slew Rate Field Reset: SLOW
    //             Slew rate control.
    //     SLOW (0) - Slow Slew Rate
    //     FAST (1) - Fast Slew Rate
    HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_WR(
            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_HYS_V(DISABLED) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUS_V(100K_OHM_PD) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUE_V(KEEP) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PKE_V(DISABLED) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_ODE_V(DISABLED) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SPEED_V(100MHZ) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE_V(40_OHM) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SRE_V(FAST));

    // Config spdif.SPDIF_OUT to pad GPIO17(R1)
    // HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17_WR(0x00000004);
    // HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_WR(0x000000B1);
    // Mux Register:
    // IOMUXC_SW_MUX_CTL_PAD_GPIO17(0x020E024C)
    //   SION [4] - Software Input On Field Reset: DISABLED
    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
    //     ENABLED (1) - Force input path of pad.
    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
    //                    Select iomux modes to be used for pad.
    //     ALT0 (0) - Select instance: esai signal: ESAI_TX0
    //     ALT1 (1) - Select instance: enet signal: ENET_1588_EVENT3_IN
    //     ALT2 (2) - Select instance: ccm signal: CCM_PMIC_READY
    //     ALT3 (3) - Select instance: sdma signal: SDMA_EXT_EVENT0
    //     ALT4 (4) - Select instance: spdif signal: SPDIF_OUT
    //     ALT5 (5) - Select instance: gpio7 signal: GPIO7_IO12
    HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17_WR(
            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO17_SION_V(DISABLED) | 
            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO17_MUX_MODE_V(ALT4));
    // Pad Control Register:
    // IOMUXC_SW_PAD_CTL_PAD_GPIO17(0x020E061C)
    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
    //     DISABLED (0) - CMOS input
    //     ENABLED (1) - Schmitt trigger input
    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
    //     100K_OHM_PD (0) - 100K Ohm Pull Down
    //     47K_OHM_PU (1) - 47K Ohm Pull Up
    //     100K_OHM_PU (2) - 100K Ohm Pull Up
    //     22K_OHM_PU (3) - 22K Ohm Pull Up
    //   PUE [13] - Pull / Keep Select Field Reset: PULL
    //     KEEP (0) - Keeper Enabled
    //     PULL (1) - Pull Enabled
    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
    //     DISABLED (0) - Pull/Keeper Disabled
    //     ENABLED (1) - Pull/Keeper Enabled
    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
    //              Enables open drain of the pin.
    //     DISABLED (0) - Output is CMOS.
    //     ENABLED (1) - Output is Open Drain.
    //   SPEED [7:6] - Speed Field Reset: 100MHZ
    //                 NOTE: Read Only Field
    //                 The value of this field is fixed and cannot be changed.
    //     TBD (0) - TBD
    //     50MHZ (1) - Low (50 MHz)
    //     100MHZ (2) - Medium (100 MHz)
    //     200MHZ (3) - Maximum (200 MHz)
    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
    //     HIZ (0) - HI-Z
    //     240_OHM (1) - 240 Ohm
    //     120_OHM (2) - 120 Ohm
    //     80_OHM (3) - 80 Ohm
    //     60_OHM (4) - 60 Ohm
    //     48_OHM (5) - 48 Ohm
    //     40_OHM (6) - 40 Ohm
    //     34_OHM (7) - 34 Ohm
    //   SRE [0] - Slew Rate Field Reset: SLOW
    //             Slew rate control.
    //     SLOW (0) - Slow Slew Rate
    //     FAST (1) - Fast Slew Rate
    HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_WR(
            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_HYS_V(DISABLED) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUS_V(100K_OHM_PD) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUE_V(KEEP) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PKE_V(DISABLED) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_ODE_V(DISABLED) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE_V(40_OHM) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SRE_V(FAST));

    // Config spdif.SPDIF_SR_CLK to pad ENET_REF_CLK(V22)
    // HW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_WR(0x00000006);
    // HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_WR(0x000000B1);
    // Mux Register:
    // IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK(0x020E01D4)
    //   SION [4] - Software Input On Field Reset: DISABLED
    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
    //     ENABLED (1) - Force input path of pad.
    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
    //                    Select iomux modes to be used for pad.
    //     ALT1 (1) - Select instance: enet signal: ENET_TX_CLK
    //     ALT2 (2) - Select instance: esai signal: ESAI_RX_FS
    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO23
    //     ALT6 (6) - Select instance: spdif signal: SPDIF_SR_CLK
    HW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_WR(
            BF_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_SION_V(DISABLED) | 
            BF_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_MUX_MODE_V(ALT6));
    // Pad Control Register:
    // IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK(0x020E04E8)
    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
    //     DISABLED (0) - CMOS input
    //     ENABLED (1) - Schmitt trigger input
    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
    //     100K_OHM_PD (0) - 100K Ohm Pull Down
    //     47K_OHM_PU (1) - 47K Ohm Pull Up
    //     100K_OHM_PU (2) - 100K Ohm Pull Up
    //     22K_OHM_PU (3) - 22K Ohm Pull Up
    //   PUE [13] - Pull / Keep Select Field Reset: PULL
    //     KEEP (0) - Keeper Enabled
    //     PULL (1) - Pull Enabled
    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
    //     DISABLED (0) - Pull/Keeper Disabled
    //     ENABLED (1) - Pull/Keeper Enabled
    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
    //              Enables open drain of the pin.
    //     DISABLED (0) - Output is CMOS.
    //     ENABLED (1) - Output is Open Drain.
    //   SPEED [7:6] - Speed Field Reset: 100MHZ
    //     TBD (0) - TBD
    //     50MHZ (1) - Low (50 MHz)
    //     100MHZ (2) - Medium (100 MHz)
    //     200MHZ (3) - Maximum (200 MHz)
    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
    //     HIZ (0) - HI-Z
    //     240_OHM (1) - 240 Ohm
    //     120_OHM (2) - 120 Ohm
    //     80_OHM (3) - 80 Ohm
    //     60_OHM (4) - 60 Ohm
    //     48_OHM (5) - 48 Ohm
    //     40_OHM (6) - 40 Ohm
    //     34_OHM (7) - 34 Ohm
    //   SRE [0] - Slew Rate Field Reset: SLOW
    //             Slew rate control.
    //     SLOW (0) - Slow Slew Rate
    //     FAST (1) - Fast Slew Rate
    HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_WR(
            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_HYS_V(DISABLED) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUS_V(100K_OHM_PD) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUE_V(KEEP) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PKE_V(DISABLED) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_ODE_V(DISABLED) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SPEED_V(100MHZ) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_DSE_V(40_OHM) | 
            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SRE_V(FAST));
}
